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TC9457F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9457F
Firmware Built In Digital Servo
The TC9457F is a firmware incorporating CD digital servo system. In addition to an LCD/LED driver, 4-channel 6-bit AD converters, and 2-wire/3-wire serial interface, it has a buzzer function, interrupt function, and 8-bit timer/counter. The CPU allows selection of the operating clock from three types of crystal oscillators (16.9344 MHz, 4.5 MHz, and 75 kHz), making interfacing with a CD easy. The CD digital servo incorporates various functions and circuits required for CD systems. These include sync separation protection and interpolation, EFM demodulation, error correction, digital equalizer for servoing, and a servo control circuit. Furthermore, it contains a 1-bit DA converter, so that when combined with the digital servo head amp TA2109F, it allows you to create a maintenance-free, extremely simple CD player system.
Weight: 1.6 g (typ.)
Features
* * CMOS-technology DTS microcontroller LSI incorporating a CD digital servo and LCD/LED driver Operating supply voltage: When CD is operating, VDD = 4.5 to 5.5 V (5.0 V typ.) When CD is turned off, VDD = 2.7 to 5.5 V (CPU operating) Current consumption: When CD is operating, IDD = 55 mA (typ.) When CD is turned off, IDD = 2 mA (typ.) (using 4.5 MHz crystal; CPU operating) When CD is turned off, IDD = 0.1 mA (using 75 kHz crystal; CPU operating) Operating temperature range: Ta = -40 to 85 C Firmware * Instruction execution time: 1.89/1.78/107 s * Crystal oscillator frequency: 16.9344 MHz/4.5 MHz/75 kHz * AD converter: 6 bits, 4 channels * LCD driver: 1/4 duty, 1/2 biased, maximum 72 segments * LED driver: 4 digits x maximum 14 segments (shared with LCD driver in software) * Timer/counter: 8 bits (timer clock selectable from INTR1, INTR2, instruction cycle, or 1 kHz) * Serial interface: 3-wire/2-wire interface (data length: 4 or 8 bits) * Buzzer: 0.625 to 3 kHz (8 types) ; 4 modes available-continuous, single, 10 Hz intermittent, and 10 Hz intermittent at 1 Hz interval * Interrupt: 1 external, 3 internal (CD subing synchronous, serial interface, 8 bits timer)
*
* *
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* CD digital servo system * Capable of decoding text data. * Sure and reliable sync pattern detection, sync signal protection, and interpolation. * Contains EFM demodulator circuit and subcode demodulator circuit. * CIRC logical equations to provide high correction capability: dual C1 correction and quadruple C2 correction. * Supports variable-speed playback. * Jitter absorbing capability of +6 frames. * Contains 16 KB RAM. * Contains Digital OUT circuit. * Contains L/R independent digital attenuators. * Audio output responds to bilingual function. * Subcode Q data is free of read timing and can be output synchronously with audio data. (LCD/OT pin switchable by a program) * Contains data slice and analog PLL (using adjustment-free VOC) circuits. * Loop gain, offset, and balance in focus and tracking servos can be automatically adjusted. * Contains RF gain automatic adjusting circuit. * Contains phase-correcting digital equalizer. * Contains coefficient RAM for digital equalizer, thus supporting various types of pickup. * Contains focus and tracking servo control circuit. * Servo control is possible in every mode available, providing fast and stable search. * Speed control method is adopted for lens and feed kick. * Contains AFC and APC circuits for disc motor CLV servo. * Contains defect and shock corrective circuit. * Contains 8 times oversampling digital filter and 1-bit DA converter. * 100 pin flat package.
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Pin Connection Diagram
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Block Diagram
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Description Of Pin Function
Pin No. 1~10 Symbol S1/OT5 ~ S10/OT14 S11/OT15 /CLCK Pin Name Function And Operation Remarks
11
LCD segment Segment signal outputs to the LCD panel. Up to 72 segments in a matrix with COM1 to COM4 can outputs /Output ports be displayed. All of the S1 to S18 pins can be switched for output ports by a program (Note 1). Also, the S15 to S18 pins each can be switched for I/O ports individually. When set for I/O ports, these pins become Nch open-drain outputs. Furthermore, the S11 to S14 and the P8-0 to P8-3 pins can be switched for use as CD signal (CLCK to IPF) input/output pins by a program. LCD segment outputs /Output ports /CD signals * CLCK : Subcodes P thru W data readout clock input/output. Selected between input and output by a command. * DATA : Subcodes P thru W data output. * SFSY : Playback system frame sync signal output.
12
S12/OT16 /DATA
13
S13/OT17 /SFSY
14
S14/OT18 /LRCK
* LRCK : Channel clock (44.1 kHz) output. It outputs a low for L channel and a high for R channel. Polarity can be inverted by a command. * BCK : Bit clock (1,4112 MHz) output.
15
S8-0/S15 /BCK
* AOUT : Audio data output. * MBOV : Buffer memory-over signal output. It outputs a high when buffer overflows. * IPF I/O ports /LCD segment outputs /CD signals : Correction flag output. When AOUT is C2 correction output, it outputs a high indicating that correction is impossible.
16
P8-1/S16 /AOUT
17
P8-2/S17 /MBOV
18
P8-3/S18 /IPF
For CD signal output, set parameters OT for output and LEDon = 1. Furthermore, when set for output ports, the buffer capability can be increased by setting the LEDon bit to 1, so that it can be used as an LED driver. These pins normally are used for LED segment outputs. Since the output ports can increment OT1 through OT18 by an instruction, data in external RAM/ROM can be accessed easily. Note 1: After a system reset, the output port shared pins are set for LCD output and the I/O port shared pins are set for I/O port input. 4-bit CMOS I/O ports. These ports can be set for input or output bit for bit by a program. These pins can be pulled up to VDD or down to GND by a program. Therefore, they can be used as key input pins. Also, when they are set for I/O port input, a change of state in this input can be used to clear the clock stop or wait mode.
21~24
P1-0~P1-3 /K0~K3
I/O port 1 /Key input ports
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Pin No. Symbol Pin Name Function And Operation Remarks
25
P3-0/DCREF
26~28
P3-1/ADIN1 ~ P3-3/ADIN3 P4-0/ADIN4/ BUZR
29
5-bit CMOS I/O ports. These ports can be set for input or output bit for bit by a program. The P3-0 to P4-0 pins serve dual purposes as analog I/O port 3 inputs for the internal 6-bit 4-channel AD converters. /AD analog The internal AD converters can complete conversion in 6 reference instruction cycles using a successive approximation voltage input method. The required pins can be set for AD analog input bit for bit by a program. P3-0 can be set for reference I/O port 3 voltage input, and the internal power supply (MVDD) can /AD analog be used for this reference voltage. voltage input The P4-0 pin serves dual purposes as a buzzer output pin. The buzzer output can be selected from 8 frequencies, I/O port 4 0.625 to 3 kHz. Each selected frequency can be output in /AD analog one of four modes: continuous, single, 10 Hz intermittent, voltage inputs and 10 Hz intermittent at 1 Hz interval. /Buzzer output Whether or not to use and how to control the AD converter and buzzer all can be set by a program. Note 2: If P3-0 is set for reference voltage input, note that although normally in a high-impedance state, this input during AD conversion becomes a 10 k load, typ. Therefore, pay careful attention to the output impedance that is input to this pin. 3-bit CMOS I/O ports. These ports can be set for input or output bit for bit by a program. These pins serve dual purposes as input or output pins for the serial interface circuit (SI0). The SI0 is a 2-wire/3-wire compatible serial interface. 4 or 8 bits of serial data, beginning with the MSB or LSB, are serially output from the SO/SDA pin at each clock edge on the SCK/SCL pin, and the data on SI1 or SI2 pin is serially input to the device. The serial clock (SCK/SCL) allows selection between the internal (450/225/150/75 kHz) and external sources and a selection of the active edge, rise or fall. Moreover, since the clock and data can be output via Nch open-drain outputs, various device controls and communication between controllers can be greatly facilitated. When an SI0 interrupt is enabled, an interrupt is generated at completion of SI0 execution and the program jumps to address 4. This is effective when high-speed serial communication is desired. All inputs to SI0 contain a Schmitt trigger circuit. Whether or not to use SI0 and how to control it all can be set by a program. Test mode control input pins. The test mode is selected when these pins are set high and normal operation is selected when they are low. These pins normally must be held low or left open (NC) when used for this purpose. (Pulldown resistors are built-in). CD control output pins.
I/O port 4 30 P4-1/S12 /Serial data input /Serial data input /output
31
P4-2/S0/SI1 /SDA
32
P4-3/SCK /SCL
/Serial clock input /output
33~38
TEST0 ~ TEST5
Test mode control inputs
* /HSO : Playback speed mode output.
High = normal speed; Low = double speed. /HSO/OT19 SPCK/OT20 SPDA/OT21 COFS/OT22 CD control signal outputs /output ports * SPCK * SPDA : Processor status signal readout clock output (176.4 kHz) : Processor status signal output.
39~42
* COFS : Correction system frame clock output (7.35 kHz). These pins can be switched for output ports by a program. 43 44 DOUT SBSY CD control input/outputs Digital output pin. Subcode block sync output pin. It outputs a high at the S1 position when subcode sync is detected.
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Pin No. 45 Symbol SBOK Pin Name Function And Operation Subcode Q data CRCC determination result output pin. It outputs a high when CRCC check is found OK. CD unit's digital block power supply pins. Normally, apply 5 V to VDD. When not using a CD (CD off), this power supply can be turned off, with only the controller power supply kept active, so that the controller alone is operating. In this case, the CDoff bit must be set to 1. When this bit is set to 1, pins 11 through 18 and pins 39 through 42 all are changed for output ports if they have been set for CD control signal input/output pins. PLL block-2 VREF pin. This pin outputs a phase error between EFM and PLCK signals. TMAX detection result output pin. Selected by command bit TMPS. Longer than preset period : Outputs P2VREF. Shorter than preset period : Low level (VSS). Within preset period : High impedance. Inverted input of low-pass filter amp. Output of low-pass filter amp. PLL block VREF pin. VCO filter pin. Analog block ground pin. DAC output pin for data slice level generation. RF signal input pin. CD control input/outputs Analog block power supply pin. RFRP signal center level input pin. RFRP zero-cross input pin. RF ripple signal input pin. Focus error signal input pin. Subbeam add signal input pin. Tracking error input pin. This input is read when tracking servo is on. Tracking error zero-cross input pin. Focus equalizer output pin. Tracking equalizer output pin. Analog reference power supply pin. RF amplitude adjusting control signal output pin. It outputs 3-level PWM signals. (PWM carrier = 88.2 kHz) Tracking balance control signal output pin. It outputs 3-level PWM signals. (PWM carrier = 88.2 kHz) Focus equalizer output pin. It outputs 3-level PWM signals. (PWM carrier = 88.2 kHz) Disc equalizer output pin. It outputs 3-level PWM signals. (PWM carrier = DSP block 88.2 kHz, synchronized to PXO) Analog reference power supply pin. (2 x VREF) Remarks
46, 75
VDD
47, 76
VSS P2VREF PDO
48 49

50
TMAX
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
LPFN LPFO PVREF VCOF AVSS SLCO RFI AVDD RFCT RFZI RFRP FEI SBAD TEI TEZI FOO TRO VREF RFGC
Analog input Analog output Analog output Analog output Analog input (Zin : command select) Analog input (Zin = 50 k) Analog input Analog input Analog input Analog input Analog input Analog input (Zin = 10 k) Analog output (2VREF to AVSS) Analog output (2VREF to AVSS)
70
TEBC
71
FMO
72 73
DMO 2VREF

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Pin No. 74 77 80 78 79 81 82 83 84 85 86 87 Symbol SEL XVSS XVDD XI XO DVSR RO DVRR DVDD DVRL LO DVSL CD control input/outputs Pin Name Function And Operation APC circuit on/off signal output pin. When laser is on, this pin goes to a high-impedance state when UHS = low and outputs a high when UHS = high. CD's crystal oscillator power supply pins. Normally, connect these pins to the power supply lines that are used in common for the VDD and VSS pins. CD's crystal oscillator input/output pins. Normally, connect 16.9344 MHz here. This clock is used as the system clock for the CD. After a system reset, it also is used as the system clock on the controller side. Therefore, all of the CD power supplies must be fed with power after a reset. R-channel DA converter unit ground pin. R-channel data forward output pin. R-channel reference voltage pin. DA converter unit power supply pin. L-channel reference voltage pin. L-channel data forward output pin. L-channel DA converter unit ground pin. NC pins. Normally, connect these pins to ground or leave them open. Pin 89 serves dual purposes as the Vpp pin of 2 an E PROM product. Therefore, when this pin is left open, 2 it can be shared with an E PROM product. Device's system reset signal input pin. The device remains reset while RESET is held low and when RESET is released back high, the CD unit becomes operational and the program starts from address 0. Normally, a system reset is asserted when a voltage of 2.7 V or more is applied to VDD when it is at 0 V (power-on reset). Therefore, this pin must be pulled high when used for this purpose. This pin is used to input a signal that requests or clears the hold mode. Normally, use this pin for CD mode select signal input or battery detection signal input. There are two hold modes : clock stop mode (crystal oscillator turned off) and a wait mode (CPU stopped). These modes are entered by executing the CKSTP and WAIT instructions, respectively. The clock stop mode can be requested by a programmed input: low level detection on HOLD pin or forced execution, and can be cleared by detecting a high on the HOLD pin or a change of state in its input signal. When the CKSTP instruction is executed, the clock generator and the CPU stop operating and the device is placed in a memory backup state. During this state, the device's current consumption is reduced to 1A or less. At the same time, the display output and CMOS output ports are automatically set low, and the Nch open-drain outputs are turned off. The wait mode is executed regardless of the input state on the HOLD pin, with the device's current consumption reduced. In this mode, the user can choose to keep only the crystal oscillator operating or have the CPU paused by programming. If the former is selected, all display outputs are set low and other pins retain their state ; if the latter is selected, all states are retained except that the CPU is temporarily stopped. This mode is cleared by a change of state in the HOLD input. Remarks
88, 89
NC
90
RESET
Reset input
91
HOLD
Hold mode control input
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Pin No. Symbol Pin Name Function And Operation External interrupt input pin. When the interrupt facility is enabled and a pulse of 1.11 to 2.22 s in duration is applied to this pin, an interrupt is generated and the program jumps to address 1. Input logic and the active edge (rise or fall) can be selected for each interrupt input. Also, the internal 8-bit timer clock can be chosen for this interrupt input, in which case it is possible to count pulses or generate an interrupt at a given pulse count (address 3). Since this pin is a Schmitt trigger type, it can be used as an input port for receiving remote control signals, etc. Crystal oscillator pins for the controller. The oscillator clock is used as the timebase for the clock facility or as the controller's system clock. Connect a 4.5 MHz or 75 kHz crystal resonator to the MXO and MXI pins. Since these pins do not contain internal feedback resistors, etc, an amp resistor or output resistor must be added external to the chip. * 75 kHz*** ROUT = 100 k, Rf = 10 M Ci = Co = 15 pF (typ.) Controller's crystal oscillator pins * 4.5 MHz*** ROUT = 0 , Rf = 1 M Ci = Co = 15 pF (typ.) When using the clock generated by the CD unit's crystal oscillator for clocking the entire device operation, fix the MXI pin to the GND level. Oscillation is stopped by executing a CKSTP instruction. Select the crystal oscillator and control its operation by a program. Note 3: When after turning on the CD unit's power supply, the controller system clock is switched from the crystal oscillator on the controller side to that on the CD side, provide an allowance time of several 10 ms for the CD unit's crystal oscillator to stabilize after it is powered on. This is necessary to prevent the controller from operating erratically. Power supply pins. Normally, apply a voltage of 4.5 to 5.5 V to VDD. In a backup state (when the CKSTP instruction executed), the device's current consumption is reduced to 1 A or less, allowing for the supply voltage to be lowered to Controller unit 2.0 V. power supply The device is reset and the program starts from address 0 pins when a voltage of 2.7 V or more is applied to this pin when it is at 0 V (power-on reset). Note 4: For reason of this power-on reset, make sure the device's power supply rise time is between 10 to 100 ms. Common signal outputs to the LCD panel. Up to 72 segments in a matrix with S1 to S18 can be displayed. Three voltage levels MVDD, VEE (1/2 MVDD), and GND are output for 83 Hz period at 2 ms intervals. After a system reset and after deassertion of a clock stop LCD common instruction, the VEE voltage is output and the DISP OFF outputs bit is set to 0 before common signals are output. /Output ports These pins can be switched for output ports by a program (Note1). In this case, the buffer capacity can be increased by setting the LEDon bit to 1, so that it can be used as an LED driver. These four pins normally are used for LED digit outputs. Remarks
92
INTR
External interrupt input
93
MXO
94
MXI
19, 96
MVDD
20, 95
MVSS
97 98 99 100
COM1/OT1 COM2/OT2 COM3/OT3 COM4/OT4

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Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage Input voltage Power dissipation Operating temperature Storage temperature Symbol VDD VIN PD Topr Tstg Rating -0.3~6.0 -0.3~VDD + 0.3 1400 -40~85 -65~150 Unit V V mW C C
Electrical Characteristics (Ta = 25C, VDD = MVDD = AVDD = DVDD = XVDD = 5 V,
2VREF = P2VREF = 4.2 V, VREF = PVREF = 2.1 V, unless otherwise specified) MVDD (CPU unit power supply)
Characteristics Symbol MVDD1 Test Circuit Test Condition When CPU and CD operating. However, MVDD VDD (Note 5) When CPU operating (CD powered off, 4.5 MHz crystal connected) (Note 5) When CPU operating (CD powered off, 75 kHz crystal connected) (Note 5) When crystal oscillator stopped (CKSTP instruction executed) (Note 5) When CPU operating (XI = 16.9344 MHz crystal connected) When CPU operating(MXI = 4.5 MHz crystal connected) When CPU operating (MXI = 75 kHz crystal connected) Standby mode (only crystal oscillating, 4.5 MHz or 75 kHz crystal connected) When crystal oscillator stopped (CKSTP instruction executed) Rf = 1 M, Rout = 0 , Ci = Co = 30 pF (Note 5, 6) Rf = 10 M, Rout = 100 k, Ci = Co = 15 pF, MVDD = 2.7~5.5 V (Note 5, 6) Crystal oscillation fmxt = 75 kHz Min 4.5 Typ. 5.0 Max 5.5 Unit
Operating supply voltage
MVDD2
4.5
5.0
5.5
V
MVDD3
2.7
5.0
5.5
Memory retention voltage range
MVHD
2.0
~
5.5
V
MVDD1 MVDD2 Operating supply current MVDD3 MVDD4 Memory retention current MIHD f MXT1 Crystal oscillation frequency f MXT2
1.0
2.0

2.0 0.75
4.0 mA 2.0
0.5
15

0.1 4.5
1.0
A MHz
75
kHz
Crystal oscillation start time
tst
1.0
s
Note 5: Guaranteed at VDD = MVDD = 4.5 to 5.5 V and Ta = -40 to 85C Note 6: Consider the crystal resonator used in your system when determining constants, etc.
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VDD (CD unit power supply)
Characteristics Operating supply voltage Operating supply current Crystal oscillation frequency Symbol VDD IDD fXT Test Circuit Test Condition MVDD VDD (Note 5) Min 4.5 Typ. 5.0 50 16.9344 Max 5.5 60 Unit V mA MHz
When 16.9344 MHz crystal connected Rout = 0 , Ci = Co = 15 pF (Note 5, 6)
Note 5: Guaranteed at VDD = MVDD = 4.5 to 5.5 V and Ta = -40 to 85C Note 6: Consider the crystal resonator used in your system when determining constants, etc.
LCD Common Output (COM1/OT1 to COM4/OT4)
Characteristics Symbol IOH2 High level IOH5 Output current IOL2 Low level IOL5 Output voltage 1/2 level VBS Test Circuit Test Condition VOH = 4.5 V (When LCD output, settings OT output, LEDon = 0) VOH = 4.5 V (Settings OT output, LEDon = 1) VOL = 0.5 V (When LCD output, settings OT output, LEDon = 0) VOL = 0.5 V (Settings OT output, LEDon = 1) Nonloaded (when LCD output) Min -0.1 Typ. -0.2 Max Unit
-20 0.1
-40 0.2
mA
4 2.1
10 2.3
2.5 V
Segment Output (S1/OT4 to S10/OT14, S11/OT15 to P8-0/S14 to P8-3/S18)
Characteristics Symbol IOH1 High level IOH4 Output current IOL1 Low level IOL5 Input leakage current High level Input voltage Low level VIL (P8-0 to P8-3) ILI VIH Test Circuit Test Condition VOH = 4.5 V (When LCD output, settings OT output, LEDon = 0) VOH = 4.5 V (Settings OT output, LEDon = 1, I/O port) VOL = 0.5 V (When LCD output, settings OT output, LEDon = 0) VOL = 0.5 V (Settings OT output, LEDon = 1, I/O port) VIH = 5.0 V, VIL = 0 V (P8-0 to P8-3) (P8-0 to P8-3) Min -0.05 Typ. -0.1 Max Unit
-2
-4
mA
0.05
0.1
5
10

MVDD x 0.8 0
~ ~
1.0 MVDD MVDD x 0.2
A
V
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I/O Ports (P1-0 to P4-3)
Characteristics High level Output current Low level Symbol IOH3 IOL3 IOL5 Input leakage current High level Input voltage Low level Input pullup/down resistance VIL RIN1 (P1-0 to P1-3) When pulldown, pullup are set. ILI VIH Test Circuit Test Condition VOH = 4.5 V VOL = 0.5 V (exclude P4-1, 2, 3 pin) VOL = 0.5 V (P4-1, 2, 3 pin) VIH = 5.0 V, VIL = 0 V Min -1 1.5 4 MVDD x 0.8 0 25 Typ. -2 3.0 10 ~ ~ 50 Max 1.0 MVDD MVDD x 0.2 120 V A mA Unit
k
HOLD , INTR Input Port, RESET Input
Characteristics Input leakage current High level Input voltage Low level VIL3 Symbol ILI VIH3 Test Circuit Test Condition VIH = 5.0 V, VIL = 0 V Min MVDD x 0.8 0 Typ. ~ ~ Max 1.0 MVDD MVDD x 0.2 V Unit A
A/D Converter (ADIN1 to ADIN4)
Characteristics Analog input voltage range Resolution Overall conversion error Analog input leakage Symbol VAD VRES ILI Test Circuit Test Condition ADIN to ADIN4 VIH = 5.0 V, VIL = 0 V (ADIN1 to ADIN4) Min 0 Typ. ~ 6 0.5 Max MVDD 4.0 1.0 Unit V bit LSB A
DATA, SFSY, LRCK, BCK, AOUT, MBOV, IPF Outputs and CLCK Input/Output
Characteristics High level Output current Low level IOL5 ILI High level Input voltage Low level VIL (CLCK) VIH Symbol IOH4 Test Circuit Test Condition VOH = 4.5 V (Settings OT for output, LEDon = 0) VOL = 0.5 V (Settings OT for output, LEDon = 0) VIH = 5.0 V, VIL = 0 V (CLCK) (CLCK) Min -2.0 Typ. -4.0 Max mA 5 10 Unit
Input leakage current

MVDD x 0.8 0
~ ~
1.0 MVDD MVDD x 0.2
A
V
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DOUT, SBSY, SBOK, SEL, HSO, SPCK, SPDA, COFS Outputs
Characteristics Output voltage High level Low level Symbol IOH4 IOL4 Test Circuit Test Condition VOH = 4.5 V VOL = 0.5 V Min -2 2 Typ. -4 4 Max Unit mA
PDO, TMAX, RFGC, TEBC, DMO Outputs
Characteristics Output voltage High level Low level Symbol IOH6 IOL4 Test Circuit Test Condition VOH = 3.8 V VOL = 0.5 V Min -1.0 3.0 Typ. -2.0 6.0 Max Unit mA
Propagation Delay Time (AOUT, SPDA, DATA, SBSY, SBOK)
Characteristics Propagation delay time High level Low level Symbol tpLH tpHL Test Circuit Test Condition Min Typ. 10 10 Max Unit ns
1bit DA Converter
Characteristics Noise distortion S/N ratio Dynamic range Crosstalk Analog output level Symbol THD + N S/N DR CT DACout Test Circuit Test Condition 1 kHz sine-wave, full-scale input 1 kHz sine-wave, -60 dB input conversion 1 kHz sine-wave, full-scale input 1 kHz sine-wave, full-scale input Min 90 85 1200 Typ. -85 98 90 -90 1250 Max -78 -85 1300 Unit dB dB dB dB mVrms
Other
Characteristics Input pulldown resistance XI amp feedback resistance Symbol RIN2 RfXT Test Circuit Test Condition (TEST0 to TEST5) (XI-XO) Min 1 Typ. 10 2 Max 4 Unit k M
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Package Dimensions
Weight: 1.6 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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